IPM6220
TM
P RE L I M I NA R Y
Data Sheet
July 2000
File Number
4903
Multi-Output System Electronics Regulator for Mobile PCs
The IPM6220 provides the power control and protection for five output voltages required in high-performance notebook PC applications. The IC integrates three fixed frequency pulse-width-modulation (PWM) controllers and two linear regulators along with monitoring and protection circuitry into a single 24 lead SSOP package. The two PWM controllers regulate the system main +5V and +3.3V voltages with synchronous-rectified buck converters. Synchronous rectification and hysteretic operation at light loads contributes to a high efficiency over a wide range of load variation. Efficiency is even further enhanced by using FETs rDS(ON) as a current sense resistor. Feed-forward ramp modulation, current mode control scheme, internal feed-back compensation provide fast and firm transients handling when powering advanced CPUs and chip sets. The third PWM controller regulates output voltage of +12V boost converter. Two linear regulators provide +5-ALWAYS and +3.3-ALWAYS low current outputs required by the notebook system controller. The IPM6220 monitors all the output voltages. A single PowerGood signal is issued when soft start is completed and all outpovervoltage protection latches the chip off to prevent output voltages from going above 115% of their settings. Undervoltage protection latches the chip off when any of the output drops below 75% of its setting value after soft-start sequence is completed. The PWM controller's over-current circuitry monitor the output currents by sensing the voltage drop across the lower MOSFETs. If precision current-sensing is required, an external current-sense resistors may optionally be used.
Features
* Provides Five Regulated Voltages - +5V-ALWAYS - +3.3V-ALWAYS - +5V-MAIN - +3.3V-MAIN - +12V * High Efficiency Over Wide Load Range - Synchronous Buck Converters on Main Outputs - Hysteretic Operation at Light Load * No Current-Sense Resistor Required - Uses MOSFET's rDS(ON) - Optional Current-Sense Resistor for Precision Overcurrent * Operates Directly From Battery 5.6V to 24V Input * Input Undervoltage Lock-Out (UVLO) * Excellent Dynamic Response - Combined Voltage Feed-Forward and Current Mode Control * Power-Good Output Voltages Monitor * Out of Phase Clock Generator * Separate Shutdown Pins for Advanced Configuration Power Interface (ACPI) Compliance * 300kHz Fixed Switching Frequency * Thermal Shutdown
Applications
* Mobile PCs * Hand-Held Portable Instruments
Pinout
IPM6220 (SSOP) TOP VIEW
VBATT 1 3.3V-ALWAYS 2 BOOT2 3 UGATE2 4 PHASE2 5 5V-ALWAYS 6 LGATE2 7 PGND2 8 ISEN2 9 VSEN2 10 SDWN2 11 PGOOD 12 24 BOOT1 23 UGATE1 22 PHASE1 21 ISEN1 20 LGATE1 19 PGND1 18 VSEN1 17 SDWN1 16 GATE3 15 VSEN3 14 GND 13 SDWNALL
Related Literature
* Technical Brief TB363 "Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)"
Ordering Information
PART NUMBER IPM6220CB TEMP. (oC) 0 to 70 PACKAGE 24 Ld SSOP PKG. NO. M24.15-P
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright (c) Intersil Corporation 2000
IPM6220 - PRELIMINARY Generic Mobile Power System Diagram
+VBATT
PROCESSOR SDWN1 SDWN2 5V-MAIN 3.3V-MAIN 5V-ALWAYS VI/O C8051 VID CODE SDWN ENABLE I/O CLOCK RESET VCORE
P CORE
IPM6220
3.3V-ALWAYS 12V
IPM6210
VCLOCK PGOOD PGOOD
SDWNALL ON/OFF
2
IPM6220 - PRELIMINARY
Absolute Maximum Ratings
Input Voltage, VBATT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +30.0V Phase, Isen and SDWNALL Pins. . . . . . . . . . . . GND-0.3V to +30.0V BOOT and UGATE Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +35.0V IBOOT1,2 with Respect to PHASE1,2 . . . . . . . . . . . . . . . . . . . . +7.0V SDWN1, SDWN2 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V All other pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.3V to 15V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) SSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 SSOP Package (with 3 in2 of copper) . . . . . . . . . . . TBD Thermal Resistance (Typical, Note 1) JC (oC/W) SSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28.5 Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (SSOP - Lead Tips Only)
Recommended Operating Conditions
Input Voltage, VBAT . . . . . . . . . . . . . . . . . . . . . . . . . +5.6V to +24.0V Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC Junction Temperature Range . . . . . . . . . . . . . . . . . . . . 0oC to 125oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER VCC SUPPLY VBATT Quiescent Current Standby Current Shutdown Current INPUT UVLO Rising VBATT Threshold Falling VBATT Threshold OSCILLATOR PWM1,2 Oscillator Frequency Ramp Amplitude, Peak to Peak Ramp Offset Ramp/VBAT Gain REFERENCE AND SOFT START Internal Reference Voltage Reference Voltage Accuracy Soft-Start Current During Startup PWM 1 CONVERTER, 5V MAIN Output Voltage Load Regulation Undervoltage Shutdown Level
Recommended Operating Conditions, Unless Otherwise Noted. Refer to Figures 1, 2 and 3 SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
5.6 ICC ICCSB ICCSN LGATE1, LGATE2, UGATE1, UGATE2, GATE3 Open -
14 -
24 1.4 60 10
V mA A A
4.4 3.9
4.5 4.0
4.6 4.1
V V
Fc1,2 VR1 VROFF GRB VREF ISS VOUT1 100mA < IVOUT1 < 5.0A; 5.6V < VBATT < 24.0V VUV1 VOC1 VOVP1 VHYST1 VOUT2 100mA < IVOUT2 < 5.0A; 5.6V255 -
300 2 0.5 125
345 -
kHz V V mV/V
-1.0 -
2.5 5
+1.0 -
V % A
4.9 -2.0 5.75 TBD
4.97 -0.6 -
5.1 +2.0 3.75 TBD -
V % V V V V
Overcurrent Comparator Threshold Overvoltage Shutdown Switchover to Hysteretic Operation Threshold PWM 2 CONVERTER, 3.3V MAIN Output Voltage Load Regulation Undervoltage Shutdown Level Overcurrent Comparator Threshold
3.234 -2.0 -
3.29 -0.3 -
3.366 +2.0 2.48 TBD
V % V V
3
IPM6220 - PRELIMINARY
Electrical Specifications
PARAMETER Overvoltage Shutdown Switchover to Hysteretic Operation PWM1, 2 CONTROLLER GATE DRIVERS Upper Drive Source Current Upper Drive Pullup Resistance Upper Drive Sink Current Upper Drive Pulldown Resistance Lower Gate Source Current Lower Drive Pullup Resistance Lower Gate Sink current Lower Drive Pulldown Resistance PWM 3 CONVERTER Output Voltage Load Regulation Undervoltage Shutdown Level Overcurrent Shutdown Overvoltage Shutdown PWM3 Oscillator Frequency Ramp Amplitude, Peak to Peak Maximum Duty Cycle PWM 3 CONTROLLER GATE DRIVERS Source, Sink Current Pullup, Pulldown Resistance 5V-ALWAYS AND 3.3V-ALWAYS Linear Regulator Accuracy Maximum Output Current Overcurrent Shutdown Undervoltage Shutdown Bypass Switch rDS(ON) POWER GOOD AND CONTROL FUNCTIONS Power Good Threshold for PWM1 and PWM2 VPGD1 Threshold Voltage VPWM2 Threshold Voltage PGOOD Leakage Current PGOOD Voltage Low PGOOD Min Pulse Width SDWN1, 2,ALL- Low (OFF) SDWN1, 2, - High (ON) SDWNALL - High (ON) VPG1 VPG2 IPGLKG VPGOOD TPGmin VPULLUP = 5.0V IPGOOD = -4mA -14 4.3 2.8 10 2.0 3.0 -12 4.4 2.9 -10 4.5 3.0 10 0.5 0.8 % V V A V s V V V 75 1 5.6V < VBATT < 24V; 0 < Iload < 50mA -2.0 50 100 +2.0 % mA mA % I3G R3G 0.5 3 5 A VUV3 Ioc3 VOVP3 FC3 VR3 VOUT3 Determined by external resistor divider 10mA < IVOUT3 < 120mA 2s delay Maximum current which causes undervoltage shutdown 9 -2.0 120 17.5 85 12 100 2 33 15 2.0 9 360 115 V % V mA V kHz % I2UGON R2UGPUP I2UGOFF R2UGPDN I2LGON R2LGPUP I2LGOFF R2LGPDN 0.5 3 0.75 2 0.5 3 1 1.5 10 10 5 5 A A A Recommended Operating Conditions, Unless Otherwise Noted. Refer to Figures 1, 2 and 3 (Continued) SYMBOL VOVP2 VHYST1 TEST CONDITIONS MIN 3.80 TBD TYP MAX UNITS V V
4
Block Diagram
VSEN3 GATE3 VBATT GND HGDR1 HI CLK1 BOOST CONTROLLER RAMP 2 CLK RAMP 1 POWER-ON RESET (POR) CLK2 CLK1 GATE LOGIC 1 POR DEADT PWM/HYST BOOT2 UGATE2 PHASE2 HGDR2 HI SHUTOFF HYST COMP1 + OC COMP1 PWM LATCH 1 VCC QD R Q< + OC LOGIC1 + +EA1 + REF1 -+ VSEN1 PWM ON HYST ON LO OVP1 PGND1 GATE CONTROL VCC LGDR1 LGATE1 SHUTOFF PHASE1 BOOT1 UGATE1
+
EA2 VSEN2 + +REF2 + LGATE2 R1 = 20K ISEN2 +
-+
+
SDWN
+
5
GATE CONTROL VCC LGATE2 PGND2 LGDR2 LO OVP2 HYST COMP2 CLK2 OC COMP2 2.8V OC LOGIC2 PWM VCC LATCH 2 DQ R IPM6220 - PRELIMINARY
CLK1
VOLTSECOND CLAMP
FFBK1 LGATE1
+ - FAST FEEDBACK COMP1 LGATE1 R1 = 20K ISEN1 + POR SDWN1
VSEN1 SDWN
REFERENCE REF1 REF2 5V-ALWAYS AND SOFT START
SDWN2
SDWNALL
FIGURE 1.
IPM6220 - PRELIMINARY Functional Pin Description
VBATT (Pin 1)
Supplies all the power necessary to operate the chip. IC starts to operate when voltage on this pin exceeds 4.5V and stops to operate when voltage on this pin drops below 4.0V. Also provides battery voltage to the oscillator for feedforward rejection of the input voltage variation.
VSEN1, VSEN2 (Pin 18, 10)
These pins are connected to the main outputs and provide voltage feedback signal for respective PWM controllers. The PGOOD and OVP circuits use these signals to report output voltage status and for overvoltage protection.
SDWN2 (Pin 11)
This pin provides enable/disable function and soft start for PWM2 controller. Controller is enabled when this pin is pulled high and SDWNALL is high too. Controller is off when the pin is pulled to the ground. To realize the soft-start function, terminate this pin with a capacitor. Soft-start time can be obtained from the following equitation.
3.5V x Css2 Tss1 = --------------------------------5A
3.3V-ALWAYS (Pin 2)
Output of 3.3V-AlWAYS linear regulator.
5V-ALWAYS (Pin 6)
Output of 5V-ALWAYS linear regulator.
BOOT1, BOOT2 (Pins 24 and 3)
Through these pins power is supplied to the upper MOSFET drivers of PWM1 and PWM2 converters. Connect these pins to respective junctions of bootstrap capacitors with the cathodes of the bootstrap diodes. Anodes of the bootstrap diodes are connected to pin 3, 5V-ALWAYS.
PGOOD (Pin 12)
PGOOD is an open drain output used to indicate the status of the PWM converters' output voltages. This pin is pulled low when any of the outputs except PWM3 (+12V) is not within 10% of respective nominal voltages, or when PWM3 (+12V) is not in between its undervoltage and overvoltage thresholds.
UGATE1, UGATE2 (Pins 23 and 4)
These pins provide the gate drive for the upper MOSFETs. Connect UGATE pins to the respective PWM converter's upper MOSFET gate.
SDWNALL (Pin 13)
This pin provides enable/disable function for all outputs. The chip is completely disabled, no output is present when this pin is pulled to the ground. When this pin is pulled high, 5V-ALWAYS and 3.3-ALWAYS outputs are regulated. Status of the other outputs depends on SDWN1 and SDWN2.
PHASE1, PHASE2 (Pins 22 and 5)
The so called PHASE points are the junction points of the upper MOSFET sources, output filter inductors, and lower MOSFET drains. Connect the PHASE pins to the respective PWM converter's upper MOSFET source.
GND (Pin 14)
Signal ground for the IC. All voltage levels are measured with respect to this pin.
ISEN1, ISEN2 (Pins 21 and 9)
These pins are used to monitor the voltage drop across the lower MOSFETs for current feedback and over-current protection. For precise current detection these inputs could be connected to optional current sense resistors placed in series with sources of the lower MOSFETs. To set the gain of the current sense amplifier, resistor should be placed in series with each of those inputs. Value of the resistor required can be obtained from the following equation:
20k * Iosc * Rcs R si = -------------------------------------------Vth
VSEN3 (Pin 15)
This pin provides voltage feedback signal for PWM3 controller. The PGOOD and OVP circuits use this pin to report output voltage status and for overvoltage protection. Also, this pin is used to independently disable PWM3 controller when not used. Connect this pin to 5V-ALWAYS if the boost converter is not populated in your design.
GATE3 (Pin 16)
This pins drives the boost MOSFET.
where: Iosc - desired overload current; Rcs - either rDS(ON) of the lower MOSFET, or the value of the optional current sense resistor; Vth - threshold of the current protection circuitry.
SDWN1 (Pin 17)
This pin provides enable/disable function and soft-start for PWM1 controller. Controller is enabled when this pin is pulled high and SDWNALL is high too. Controller is off when the pin is pulled to the ground. To realize the soft-start, terminate this pin with a capacitor. Soft-start time can be obtained from the following equation.
3.5V x Css1 Tss1 = --------------------------------5A
LGATE1, LGATE 2 (Pins 20 and 7)
These pins provide the gate drive for the lower MOSFETs. Connect the lower MOSFET gate of each converter to the corresponding pin.
PGND1, PGND2 (Pins 19 and 8)
These are the power ground connection for PWM1 and PWM2 converters, respectively. Tie each lower MOSFET source to the corresponding pin.
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IPM6220 - PRELIMINARY Description
Operation
The IIPM6220 addresses system electronics power needs of modern notebook and sub-notebook PCs. The IC integrates control circuits for two synchronous buck converters for +5.0V and +3.3V busses, two linear regulators for 3.3V-ALWAYS and 5V-ALWAYS, and control circuit for +12V boost converter. The PWM converters use the same clock generator with two out-of-phase outputs. This reduces input current ripple and requirements to the input filter. The +12V boost controller uses 100kHz clock derived from the main clock. This controller uses front edge PWM scheme with maximum duty factor limited to 33%. The chip has three input lines SDWN1, SDWN2 and SDWNALL for advanced control power interface (ACPI) to allow turn on and off all outputs, as well as independently control +3.3V and +5V outputs. To maximize efficiency, current sense technique based on MOSFET rDS(ON) voltage drop is used. If accurate current protection is desired, current sense resistors can optionally be used. Light load efficiency is enhanced by a hysteretic mode of operation which is automatically engaged when inductor current becomes discontinuous. the converter continuously delivers power about two times the nominal without significant drop in the output voltage. To eliminate this, the time delay circuit (8:1 counter which counts the clock cycles) is activated when the overcurrent condition is detected for the first time. This limits the inductor current buildup and essentially switches the converter into current regulation mode for a short period of time (eight clock cycles). If after the delay the overcurrent condition is still present, the converter shuts down. If not the normal operation restores. This overcurrent scheme has been proven to be very robust in applications like portable computers where fast inductor current buildup is common due to a big difference between input and output voltages and a low value of the inductor.
Operation Mode Control
The mode control circuit changes the converter's mode of operation depending on the level of the load current. At nominal current converter operates in fixed frequency PWM mode. When the load current drops lower than the critical value, inductor current becomes discontinuous and the operation mode is changed to hysteretic. The mode control circuit consists of a flip-flop which outputs provide HYST and NORMAL signals. These signals inhibit normal PWM operation and activate hysteretic comparator and diode emulation mode of the synchronous FET. The inputs of the flip-flop are controlled by outputs of two delay circuits, which constantly monitor output of the phase node comparator. High level on the comparator output during PWM cycle is associated with continuous mode of operation. The low level - corresponds to the discontinuous mode of operation. When the low level on the comparator output is detected eight times in a row, the mode control flipflop is set and converter is commanded to operate in the hysteretic mode. If during this pulse counting process the comparator's output happens to be high, the counter of the delay circuit will be reset and circuit will continue to monitor for eight low level pulses in a row from the very beginning.
TABLE 1. POWER CONTROL 3V AND 5V ALWAYS 0 1 1 1 1 3V MAIN 0 0 0 1 1
3.3V and 5V Architecture
Main outputs are generated from the unregulated DC source by two independent synchronous buck converters. IC integrates all the components required for output adjustment and feedback compensation significantly reducing the number of external parts. These buck PWM controllers are identical and employ fixed frequency current mode control scheme with addition of feed-forward ramp programming for better rejection of the input voltage variation. They use out-off-phase sequences from the same unadjusted frequency clock oscillator to reduce input current ripple.
Current Sensing and Overcurrent Protection
Both PWM converters employ the lower MOSFET on-state resistance, rDS(ON) as a current sensing element. This technique eliminates need in a current sense resistor and power losses usually associated with it. The sensed voltage drop is used for the current feedback and the overcurrent protection. The rDS(ON) voltage drop is sampled after about 200ns after the lower MOSFET is turned on. The sampled voltage after amplification is compared with internally set overcurrent threshold. To accommodate wide range of the rDS(ON) variation, the value of the overcurrent threshold should represent overload current about 180% of the nominal value. This could lead to the situation where 7
SDWNALL 0 1 1 1 1
SDWN1 X 0 1 0 1
SDWN2 X 0 0 1 1
5V MAIN 0 0 1 0 1
IPM6220 - PRELIMINARY
the soft start capacitors can be calculated from the following expression.
t
VOUT
5A x t SS Css = -------------------------3.5V
t
IIND
PHASE COMP 12345 678 MODE OF OPERATION PWM HYSTERETIC
Where: tSS - is a desired soft start time, and 3.5V is a voltage on the soft start capacitor when undervoltage protection is enabled.
t
t
By varying the values of soft start capacitors it is possible to provide sequencing of the main outputs at startup. Gate Control Logic
The gate control logic translates generated PWM control signals into the MOSFET gate drive signals providing necessary amplification, level shift and shoot-trough protection. Also, it bears some functions that help optimize the IC performance over a wide range of the operational conditions. As MOSFET switching time can very dramatically from type to type and with the input voltage, gate control logic provides adaptive dead time by monitoring gate voltages of both upper and lower MOSFETs.
FIGURE 2.
The circuit which restores normal PWM operation mode works in the same way and is looking for eight in a row high level pulses on the comparator's output. If during this counting process the comparator's output happens to be low, the counter will be reset and the mode control flip-flop will not change the state. The operation mode will only be changed when eight pulses in a row fill the counter. This technique prevents jitter and chatter of the operation mode at the load levels close to the critical.
12V Converter Architecture
The 12V boost converter generates its output voltage from the main 5V output. An external inductor, a diode and a capacitor are required to complete the circuit. The output signal is fed back to the controller via an external resistive divider. The divider allows to adjust the output voltage as necessary. For example, to accommodate the linear regulator if higher level of regulation is required. The boost controller can be disabled in the systems where there is no need for 12V power by connecting VSEN3 pin to 5V-ALWAYS rail. The control circuit for the 12V converter consists of a 3:1 frequency divider which drives a ramp generator and resets a PWM latch (Figure 2). The length of the CLK/3 pulses is equal to the period of the main clock. Thus, duty factor of the pulse sequence after the divider is limited to 1/3. An output of a non-inverting error amplifier is compared with the rising ramp voltage. When the ramp voltage becomes higher than the error signal, the PWM comparator sets the latch and the output of the gate driver is pulled high. The rising edge of the CLK/3 pulses resets the latch and pulls the output of the gate driver low. Operation of the circuit repeats after two idle periods of the main clock.
Light Load (Hysteretic) Operation
In the light load (hysteretic) mode the output voltage is regulated by the hysteretic comparator which forces the upper gate driver high when the output voltage drops lower the certain level. When the output voltage rises above the set point the upper gate driver is inhibited. Voltage on the non-inverting input of the hysteretic comparator is a reference voltage with a small addition of the clock frequency pulses. Such a scheme allows to synchronize the upper MOSFET turn-on with the main clock and contributes positively to the seamless transition between the operation modes.
3.3V and 5V Soft Start, Sequencing and Standby
The 5V and 3.3V converters are enabled if SDWN1 and SDWN2 are high (open) and SDWNALL is also high. The standby mode is defined as a condition when SDWN1 and SDWN2 are low and PWM converters are disabled but SDWNALL is high (3.3V-ALWAYS and 5V-ALWAYS outputs are enabled). Soft start of the 3.3V and 5V converters is accomplished by means of the capacitors connected from pins SDWN1 and SDWN2 to the ground. In conjunction with pull up to +VCC 5A current sources they provide controlled rise of the voltage on these pins. The output voltage of the converter should reach the regulation before the voltage on the soft start capacitor reaches the threshold of 3.5V. The value of
8
IPM6220 - PRELIMINARY
VSEN3 + EA3 GATE3 PWM PWM COMPARATOR LATCH 3 SQ RAMP + RQ
REF CLK/3 CLK DIVIDER 3:1
CLK/3
RAMP GENERATOR
The 12V converter starts to operate at the same time as the 5V converter. The softly rising voltage on the 5V output accompanied with limited to 33% maximum duty factor provides softly rising 12V output. The total capacitance on the 12V output should be chosen appropriately, so that the output voltage can buildup higher than the undervoltage limit (9V) during the soft start time in order to avoid triggering of the undervoltage protection.
Over Temperature Protection
CLK t
CLK/3 RAMP VEA3 GATE3
t t
The chip incorporates an over temperature protection circuit that shuts all the outputs down when the die temperature of 150oC is reached. Normal operation restores at the die temperatures below 125oC trough the full soft-start by cycling the input voltage.
3V-ALWAYS, 5V-ALWAYS Linear Regulators
The 3.3V-ALWAYS and 5V-ALWAYS outputs are derived from the battery voltage and are the first voltages available in the notebook when the power button is pushed down (Figure 2). The 5V-ALWAYS output is generated directly from the battery voltage by a linear regulator and is used to power the chip itself, the CPU regulator and their gate drivers. The 3.3V-ALWAYS output is used to power the keyboard controller and is generated from the 5V-ALWAYS output. The total current capability of these outputs is 50mA. When the system 5V rail is enabled and regulated, the 5V-ALWAYS output is connected to it via an internal 1 switch. Simultaneously, the 5V-AWAYS linear regulator is disabled to protect the chip from the excessive power dissipation.
t
FIGURE 3.
The fact that the maximum duty factor of the converter is limited to 1/3 allows for guaranteed discontinuous inductor current operation over the all operation conditions. The inductor should be kept lower some critical value.
Vinmin 2 x Dmax 2 x Ro Lmax = ---------------------------------------------------------------2 x Vo 2 x F
where, Vinmin -- minimum input voltage; Dmax=1/3 -maximum duty factor; Ro -- nominal load resistance; Vo -nominal output voltage; F -- the switching frequency. The boost converter with the limited duty factor in the discontinuous inductor current mode can deliver to the load and correspondingly draw from the source only certain amount of energy. The output voltage starts to drop when the maximum duty factor is reached.
Ro Vo = Vin x Dmax x ---------------------2xLxF
IPM6220 DC-DC Converter Application Circuit
Figure 4 shows an application circuit of a power supply for a notebook PC microprocessor system. The power supply provides +5V_ALWAYS, +3.3V_ALWAYS, +5.0V, +3.3V, and +12.0V from +5.6-24VDC battery voltage. For detailed information on the circuit, including a Bill-of-Materials and circuit board description, see Application Note ANXXXX. Also see Intersil's web site (www.intersil.com) or Intersil AnswerFAX (321-724-7800) for the latest information.
Thus, providing automatic output overcurrent limiting. If the value of the inductor is chosen properly, the output current twice as high as a nominal will pull the output voltage down to the point were the undervoltage protection comes into effect.
9
IPM6220 - PRELIMINARY
+5-24VIN GND C1 56F C7-8 2x1F
CR1 BAT54WT1 VBATT +3.3V-ALWAYS (50mA) + +5V-ALWAYS (50mA) + C2 10F 23 5V-ALWAYS C3 68F 6 22 21 BOOT2 C4 0.22F +3.3V (5A) Q3 ITF86130SK8 UGATE2 PHASE2 L1 8H + C5 680F Q4 ITF86130SK8 R1 680 LGATE2 PGND2 VSEN2 SDWN2 C6 0.01F PGOOD 12 14 GND 13 SDWNALL 7 8 10 11 15 17 VSEN3 SDWN1 C13 0.01F R4 24K9 16 GATE3 ISEN2 4 5 9 18 VSEN1 Q5 HUF76113SK8 CR3 MBRS130 + R3 97K6 C11,C12 2x68F UGATE1 PHASE1 ISEN1 R2 680 20 19 LGATE1 PGND1 Q2 ITF86130SK8 L2 8H + L3 6.8H C10 680F +5V (5A) 1 3.3V-ALWAYS 2 24 BOOT1 C9 0.22F
Q1 ITF86130SK8
CR2 BAT54WT1 3
IPM6220
FIGURE 4. APPLICATION CIRCUIT
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IPM6220 - PRELIMINARY Shrink Small Outline Plastic Packages (SSOP/QSOP)
N INDEX AREA E H
M24.15-P
24 LEAD SHRINK NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL MIN 0.053 0.007 0.008 0.007 0.337 0.149 MAX 0.069 0.011 0.012 0.010 0.344 0.157 MILLIMETERS MIN 1.35 0.178 0.203 0.178 8.56 3.78 MAX 1.75 0.279 0.305 0.254 8.74 3.99 NOTES 1 2 1.27 24 8o 0o 8o 3 4 Rev. 1 7/96
1
2
3 SEATING PLANE D A
A
L
A1 B C
h x 45o
D E
e
B 0.17(0.007) M A1 0.10(0.004) C
e H h L N
0.025 BSC 0.228 0.015 0.016 24 0o 0.050 0.244
0.635 BSC 5.79 0.38 0.41 6.20
NOTES: 1. Dimension "D" does not include mold flash, protrusions or gate burrs. 2. Dimension "E" does not include interlead flash or protrusions. 3. "L" is the length of terminal for soldering to a substrate. 4. "N" is the number of terminal positions. 5. Terminal numbers are shown for reference only. 6. Controlling dimension: INCHES. Converted millimeter dimensions are not necessarily exact.
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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Sales Office Headquarters
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